FPGA based Novel High Speed DAQ System Design with Error Correction

摘要

Present state of the art applications in the area of high energy physicsexperiments (HEP), radar communication, satellite communication and bio medicalinstrumentation require fault resilient data acquisition (DAQ) system with thedata rate in the order of Gbps. In order to keep the high speed DAQ systemfunctional in such radiation environment where direct intervention of human isnot possible, a robust and error free communication system is necessary. Inthis work we present an efficient DAQ design and its implementation on fieldprogrammable gate array (FPGA). The proposed DAQ system supports high speeddata communication (~4.8 Gbps) and achieves multi-bit error correctioncapabilities. BCH code (named after Raj Bose and D. K. RayChaudhuri) has beenused for multi-bit error correction. The design has been implemented on XilinxKintex-7 board and is tested for board to board communication as well as forboard to PC using PCIe (Peripheral Component Interconnect express) interface.To the best of our knowledge, the proposed FPGA based high speed DAQ systemutilizing optical link and multi-bit error resiliency can be considered firstof its kind. Performance estimation of the implemented DAQ system is done basedon resource utilization, critical path delay, efficiency and bit error rate(BER).